FIG. 1 is a circuit diagram showing a conventional SPDT switch shown in “High-power microwave transmit-receive switch with series and shunt GaAs FETs”, IEICE Trans. ELECTRON, February 1992.
The SPDT switch as shown in FIG. 1 has an input terminal 1a, output terminal 1b, output terminal 1c, FET (field-effect transistor) 2a, FET 2b, inductor 3a, inductor 3b, line 4 and ground 5. The FET 2a has its drain connected to the input terminal 1a, and its source connected to the output terminal 1c. The inductor 3a has its first terminal connected to the input terminal 1a, and its second terminal connected to the output terminal 1c. The line 4 has its first terminal connected to the input terminal 1a, and its second terminal connected to the output terminal 1b. The FET 2b has its drain connected to the output terminal 1b, and its source connected to the ground 5. The inductor 3b has its first terminal connected to the output terminal 1b, and its second terminal connected to the ground 5.
Next the operation will be described.
In FIG. 1, the FET 2a and FET 2b operate as switches for switching between the ON state and OFF state in response to a voltage applied to their gates. When a gate voltage with the same potential as the drain voltage and source voltage is applied to the gate of the FET 2a, the FET 2a is brought into the ON state and exhibits a resistance property. On the other hand, when a voltage less than the pinch-off voltage is applied to the gate of the FET 2a, the FET 2a is brought into the OFF state and exhibits a capacitance property. The FET 2b operates in the same manner.
FIG. 2 is an equivalent circuit diagram when the FET 2a and FET 2b in FIG. 1 are brought into the OFF state. As shown in FIG. 2, when the FET 2a is brought into the OFF state, a state arises in which a parallel connection of an OFF capacitance 9 and an OFF resistance 10 is connected in series with a parasitic inductor 8 between the drain or source 6a and the source or drain 6b of the FET 2a. The same state arises when the FET 2b is brought into the OFF state.
FIG. 3 is an equivalent circuit diagram when the FET 2a and FET 2b in FIG. 1 are brought into an ON state. As shown in FIG. 3, when the FET 2a is brought into the ON state, a state arises in which the ON resistance 7 and parasitic inductor 8 are connected in series between the drain or source 6a and the source or drain 6b of the FET 2a. The same state arises when the FET 2b is brought into the ON state.
In FIG. 1, consider the case where the FET 2a and FET 2b are brought into the OFF state, that is, when the equivalent circuit diagram of the FET 2a and FET 2b is FIG. 2. At the frequency f1 used by the SPDT switch, when the reactance component of the parasitic inductor 8 is small enough as compared with the reactance component of the OFF capacitance 9, and the OFF resistance 10 is sufficiently large, and when the relationship holds of f1=1/√{square root over ( )}(capacitance of OFF capacitance 9 of FET 2a)×(inductance of inductor 3a)=1/√{square root over ( )}(capacitance of OFF capacitance 9 of FET 2b)×(inductance of inductor 3b), the impedance of the output terminal 1b seen from the input terminal 1a becomes low, and the impedance of the output terminal 1c seen from the input terminal 1a becomes high. In this case, the high frequency signal input through the input terminal 1a is fed to the output terminal 1b. 
In addition, consider the case where the FET 2a and FET 2b are brought into the ON state in FIG. 1, that is, when the equivalent circuit diagram of the FET 2a and FET 2b is FIG. 3. In this case, the impedance of the output terminal 1b seen from the input terminal 1a becomes high, and the impedance of the output terminal 1c seen from the input terminal 1a becomes low. Thus, the high frequency signal input through the input terminal 1a is fed to the output terminal 1c. 
With the foregoing configuration, the conventional SPDT switch has the following problem. When the gate width of the FET 2a and FET 2b is increased to achieve high withstanding power, the reactance component of the parasitic inductor 8 comes to be not negligible as compared with the reactance component of the OFF capacitance 9, and the OFF resistance 10 becomes small. Accordingly, when the FET 2a and FET 2b are brought into the OFF state, the propagation loss of the high frequency signal propagating from the input terminal 1a to the output terminal 1b increases, which presents a problem of reducing the isolation of the high frequency signal from the input terminal 1a to the output terminal 1c. 
Although the conventional technique is described by way of example of the SPDT switch, an SPST switch or MPMT switch has the same problem.
The present invention is implemented to solve the foregoing problem. Therefore it is an object of the present invention to provide an SPST switch, SPDT switch and MPMT switch having characteristics of being able to achieve high withstanding power, to reduce propagation loss of the high frequency signal, and to prevent the reduction in the isolation.